1. Field of the Invention
The invention relates generally to digital frequency synthesizer apparatus, and more particularly to such apparatus employing an accumulator for synthesizing a selected frequency of a number of preselected frequencies in conjunction with a randomizer which adds random or pseudorandom values to a selectable few of the least significant bits of the accumulator.
2. Description of Related Art
In the design of radio communications systems, a continuing goal has been the design of a simple, low-cost frequency synthesizer that can provide a large library of discrete frequencies over a very wide frequency spectrum. Design efforts toward this goal have introduced an associated spectrum of spurious outputs, the minimization of which has not been entirely successful or satisfactory.
Prior art approaches have typically been too complex for commercial feasibility. Most such prior-art solutions employ digital logic and have required the use of hybrid devices such as digital-to-analog (D/A) converters, as well as table look-up devices such as sine/cosine Read Only Memories (ROM's). A primary purpose of these additional elements has been to reduce the poor output spectral quality. Such associated poor output spectral quality is mainly evidenced by the presence of a large number of unwanted or spurious line spectral components referred to commonly as "spurs."
Direct Digital Frequency Synthesis is a digital technique of frequency synthesis that is often used in phase and frequency modulation and frequency hopping schemes in spread spectrum communications. This technique is advantageous because of the speed at which frequency can be changed, the small frequency step size possible, and the digital control of phase or frequency available. An apparatus employing this technique is referred to as a Direct Digital Synthesizer or "DDS."
The output frequency of a DDS is determined by an input digital frequency control word. This frequency control word can be generated by a digital processor. Many modulation schemes can be implemented, for example, FSK, FM, PM, DPSK, etc. Thus, for example, the output frequency can be frequency modulated according to the information digitized by the processor (FSK modulation). In addition to the FSK modulation, the window of modulated frequencies can hop, thereby moving the window of modulated frequencies in a coded scheme to avoid jamming or decoding by unauthorized transceivers. It is the agility and the frequency resolution of the DDS that makes it superior to other synthesizers in such an application and gives an unauthorized transceiver less time to lock on the correct frequency and then jam or decode it. Naturally, the authorized receiver must hop to the correct frequency to receive the modulated information. The receiver's digital processor generates the correct digital control word for the receiver's DDS and subsequent down-conversion, demodulation, and decoding.
The heart of the Direct Digital Synthesizer is the accumulator. The accumulator is a digital integrator consisting of a latch and full adder with the output sum and the input digital control word as inputs to the adder. The frequency word determines the step size by which the accumulated sum is incremented. Each step represents a step or increment in phase; thus, larger frequency words result in larger steps in phase. In addition, the rate of overflow of the accumulator determines the output frequency. The output frequency is a fraction of the clock frequency; thus its spurious performance has similarities to a fractional divider. However, some frequencies are not submultiples of the clock frequency, and the accumulator overflow occurs with varying remainders left in the accumulator. The residue left in the accumulator varies the output periods such that a sequence of different output periods result. The average of this sequence of periods is the desired period and, thus, determines the output frequency. However, since this sequence of periods is also different from an ideal repetition of the exact period, spurious line frequencies or "spurs" unique to each output frequency are created. Such spurs represent departure of the output waveform from a precisely periodic signal.
If the overflow of the accumulator is used to generate a binary output, the spurious levels will be significant. The conventional method used to suppress these spurious frequencies utilizes a sine approximation technique. This technique essentially consists of the accumulator, a sine look-up table in Read Only Memory (ROM), a digital analog converter (DAC), and an output filter. The instantaneous error from an ideal sinusoidal frequency of constant period is reduced; therefore, the spurious levels are suppressed.
An alternative to such solutions is disclosed in Wheatley, U.S. Pat. No. 4,410,954. That patent discloses an apparatus for feeding a value corresponding to a selected phase increment at a clock rate to an adder, which is in mutual cooperation with an accumulator. The resultant periodic overflow of the accumulator corresponds to the selected frequency of interest. Additional cooperating apparatus is provided for generating a random sequence of values. The difference between any one of these values and the selected phase increment is less than the selected phase increment. Jitter logic is responsive to the overflow output of the accumulator to add or subtract a sequential one of the random values to or from the phase increment value as an input to the accumulator for at least one clock interval occurring within the duration between successive overflows of the accumulator. The Wheatley dithered DDS has a binary output; therefore, it has the advantage that no ROM or DAC is needed.
The Wheatley method randomly varies or dithers the accumulator at each overflow or alternate overflows such that the edges or just one edge of the binary output are dithered. The Wheatley circuit thus reduces spurs by summing a random value with a uniform distribution up to the selected phase increment or "input vector." However, the Wheatley operation introduces flat phase noise, although, in many applications, the introduced flat phase noise is within the phase noise performance margin and hence does not limit system performance, whereas the spurious performance attributable to spurs in the absence of spur reduction would limit system performance.
One disadvantage of the Wheatley circuit is that the frequency deviation density decreases with decreasing frequency offset. Hence, the deviation density is inadequate to reduce close-in spurs, i.e., those spurs near the desired frequency output.
A second disadvantage of the Wheatley circuit is the lack of flexibility in selecting between the amount of spur reduction and phase noise. Since the dither is uniform up to the input vector, a trade-off between spur reduction and phase noise is established. With Wheatley's circuit, selectability between these two performance criteria can be achieved only through selection of the clock rate, a relatively inflexible approach.